Semiconductor wafers are fabricated by selective layering, patterning and doping steps to form desired electronic devices and interconnecting circuitry. As semiconductor processing technology has advanced to compress more and more electronic devices into a smaller space, the topography of the wafer surface has become more irregular. This has lead to increasing difficulty in wafer processing. Generally, the higher the degree of planarity of the upper wafer surface, the less problems are encountered in processing. This invention specifically concerns techniques for increasing the degree of planarity of dielectric or insulating layers on semiconductor wafers.
In order to build an integrated circuit on a wafer, it is necessary to fabricate many active devices on a single substrate. Initially, each of the devices must be electrically isolated from others. But later in the fabrication sequence, specific devices must be electrically interconnected so as to implement the desired circuit functions. The electrical interconnects in early generations of bipolar integrated circuits typically consisted of a single level of metal and heavily doped diffused regions in the silicon substrate. As the technology progressed however, interconnects with multiple levels of metal became needed, resulting in more processing steps having more layers and a resulting highly irregular wafer surface topography.
Differences in elevation within a given layer, commonly referred to as "steps", can exceed two microns with current ULSI (ultra large scale integration) technology. At some point, such surfaces must be planarized to some degree to prevent the topography roughness from growing with each level. Without planarization, the microscopic canyons that result on the wafer surface from stacking of device features can lead to topography conditions that would reduce the yield of circuits to unacceptably small values.
Planarization of the intermetal dielectric layers is one of the approaches that has been taken to alleviate the problem of rough surface topography. Planarizing of dielectric materials varies in degree from no planarization to smoothing, partial or semi-planarization, complete local planarization, or complete global planarization of the wafer surface. To achieve a degree of planarizing, it is necessary that the dielectric layer being planarized be brought to a temperature sufficient to at least partially melt the material to cause flow and a resulting planarizing effect to the upper surface.
One common dielectric material is SiO.sub.2. Pure SiO.sub.2 has a very high melting point (approximately 1,200.degree. C.) such that it is not typically used in its pure form as a dielectric material for a layer which will be planarized. At a temperature of 1,200.degree. C., the substrate would potentially be damaged by adverse high temperature effects. Accordingly, materials such as SiO.sub.2 are commonly doped with other materials, such as boron and phosphorous which is such case would produce borophosphosilicate glass (BPSG). Such compositions have melting temperatures between about 800.degree. C. and 850.degree. C., depending upon boron and phosphorus concentration, which is a processing temperature which will typically not damage the wafer circuitry. BPSG is a common material for the last protective coating applied atop the wafer at the conclusion of circuit fabrication.
The typical way of planarizing a BPSG, or other dielectric layer having a melting point of 850.degree. C. or less, is to heat the wafer in an inert atmosphere at 900.degree. C. for a predetermined period of time, such as 30 minutes, to cause melting and flow. An alternate prior art process is to use rapid thermal processing (RTP) or rapid thermal annealing (RTA). Yet another alternate method includes applying a thick layer of BPSG or other dielectric and etching the layer back to produce a planarized upper surface.
This invention provides an alternate method of planarizing dielectric films having melting temperatures which are below approximately 850.degree. C.